[AArch64] Improved bitfield instruction selection.
authorGeoff Berry <gberry@codeaurora.org>
Fri, 18 Sep 2015 17:11:53 +0000 (17:11 +0000)
committerGeoff Berry <gberry@codeaurora.org>
Fri, 18 Sep 2015 17:11:53 +0000 (17:11 +0000)
commit068d9ce82714f6e3537d551c7adee1cb56abeb9e
tree49f69cb93a0f093d609cbb764679b810be28a720
parente016c66756f9a47c169c352ca900fe5b376a896a
[AArch64] Improved bitfield instruction selection.

Summary:
For bitfield insert OR matching, check both operands for larger pattern
first before checking for smaller pattern.

Add pattern for unsigned bitfield insert-in-zero done with SHL+AND.

Resolves PR21631.

Reviewers: jmolloy, t.p.northover

Subscribers: aemerson, rengolin, llvm-commits, mcrosier

Differential Revision: http://reviews.llvm.org/D12908

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@248006 91177308-0d34-0410-b5e6-96231b3b80d8
lib/Target/AArch64/AArch64ISelDAGToDAG.cpp
test/CodeGen/AArch64/bitfield-insert.ll
test/CodeGen/AArch64/xbfiz.ll