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[AArch64] Changes some SchedAlias to WriteRes for Cortex-A57.
authorChad Rosier <mcrosier@codeaurora.org>
Fri, 10 Apr 2015 13:19:27 +0000 (13:19 +0000)
committerChad Rosier <mcrosier@codeaurora.org>
Fri, 10 Apr 2015 13:19:27 +0000 (13:19 +0000)
commit0937a348d06a787d47bc5b690f188e2d741cfe5d
tree81fcbb8acfaefa7e511ada83b48084576917e5ebtree | snapshot
parent694883f0f7d1e4abe4a9785f5dd2bb145577a5a7commit | diff
[AArch64] Changes some SchedAlias to WriteRes for Cortex-A57.

Using SchedAliases is convenient and works well for latency and resource
lookup for instructions.  However, this creates an entry in
AArch64WriteLatencyTable with a WriteResourceID of 0, breaking any
SchedReadAdvance since the lookup will fail.

http://reviews.llvm.org/D8043
Patch by Dave Estes <cestes@codeaurora.org>!

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@234594 91177308-0d34-0410-b5e6-96231b3b80d8
lib/Target/AArch64/AArch64SchedA57.td diff | blob | history
C/C++ LLVM-based compilers that forbids OOTA behaviors