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(parent: a946367) | patch
ar71xx: use correct PLL configuration register bitmask for QCA956x SoC.
authorFelix Fietkau <nbd@openwrt.org>
Mon, 2 Nov 2015 18:20:51 +0000 (18:20 +0000)
committerFelix Fietkau <nbd@openwrt.org>
Mon, 2 Nov 2015 18:20:51 +0000 (18:20 +0000)
commit0b296d380807050cee0a682caf388d6d71aef435
treefad0c9bc9a79b8609ef7f0bcf9078f8bec87e2eftree | snapshot
parenta94636737197c82245ca1a346e1908ca60a89d45commit | diff
ar71xx: use correct PLL configuration register bitmask for QCA956x SoC.

Incorrect value causes clock inaccuracy as huge as 1/60.

Signed-off-by: Dmitry Ivanov <dima@ubnt.com>
Signed-off-by: Felix Fietkau <nbd@openwrt.org>
SVN-Revision: 47363
target/linux/ar71xx/patches-4.1/621-MIPS-ath79-add-support-for-QCA956x-SoC.patch diff | blob | history
LEDE/OpenWrt router OS modified for Vigilia