drm/rockchip: support setting specail pll for hdmi
In order to get lower jitter clock for hdmi tmds, Hardware
design that: direct get tmds clock from vpll, bypass vop.
This design can make hdmi good works, but also limit hdmi's
clock source, the vop which hdmi use need also assign to vpll,
and use same clock rate, it's hardware limitation.
This patch add a mechanism to select dclk's parent pll, then
can allocate correct pll for hdmi.
Change-Id: I9e3b4b6d3756c409782df0605706be4203d69a32
Signed-off-by: Mark Yao <mark.yao@rock-chips.com>
Suggested-by: Heiko Stuebner <heiko@sntech.de>