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(parent: 0803172) | patch
ioat2,3: cacheline align software descriptor allocations
authorDan Williams <dan.j.williams@intel.com>
Wed, 9 Sep 2009 00:53:04 +0000 (17:53 -0700)
committerDan Williams <dan.j.williams@intel.com>
Wed, 9 Sep 2009 00:53:04 +0000 (17:53 -0700)
commit162b96e63e518aa6ff029ce23de12d7f027483bf
tree532191d0cef7cf975b70a07b1c69a293d6f552f7tree | snapshot
parent0803172778901e24a75ab074798d98c2b7411559commit | diff
ioat2,3: cacheline align software descriptor allocations

All the necessary fields for handling an ioat2,3 ring entry can fit into
one cacheline.  Move ->len prior to ->txd in struct ioat_ring_ent, and
move allocation of these entries to a hw-cache-aligned kmem cache to
reduce the number of cachelines dirtied for descriptor management.

Signed-off-by: Dan Williams <dan.j.williams@intel.com>
drivers/dma/ioat/dma_v2.c diff | blob | history
drivers/dma/ioat/dma_v2.h diff | blob | history
drivers/dma/ioat/pci.c diff | blob | history
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