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(parent: c0b12df) | patch
Partial support for Intel SHA Extensions (sha1rnds4)
authorBen Langmuir <ben.langmuir@intel.com>
Thu, 12 Sep 2013 15:51:31 +0000 (15:51 +0000)
committerBen Langmuir <ben.langmuir@intel.com>
Thu, 12 Sep 2013 15:51:31 +0000 (15:51 +0000)
commit1f1bd9a54d25d4e2c5da13c2cae7fa5e3d8acc9f
tree6a4093eec10f724f5f8bc99e58474ecfa2ec66e8tree | snapshot
parentc0b12dfd0a83081c1ebbb55a89c7a2c1f98f1842commit | diff
Partial support for Intel SHA Extensions (sha1rnds4)

Add basic assembly/disassembly support for the first Intel SHA
instruction 'sha1rnds4'. Also includes feature flag, and test cases.

Support for the remaining instructions will follow in a separate patch.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190611 91177308-0d34-0410-b5e6-96231b3b80d8
lib/Target/X86/X86.td diff | blob | history
lib/Target/X86/X86InstrInfo.td diff | blob | history
lib/Target/X86/X86InstrSSE.td diff | blob | history
lib/Target/X86/X86Subtarget.cpp diff | blob | history
lib/Target/X86/X86Subtarget.h diff | blob | history
test/MC/Disassembler/X86/x86-64.txt diff | blob | history
test/MC/X86/x86_64-encoding.s diff | blob | history
C/C++ LLVM-based compilers that forbids OOTA behaviors