[PPC64] Add vector pack/unpack support from ISA 2.07
authorBill Schmidt <wschmidt@linux.vnet.ibm.com>
Sat, 16 May 2015 01:02:12 +0000 (01:02 +0000)
committerBill Schmidt <wschmidt@linux.vnet.ibm.com>
Sat, 16 May 2015 01:02:12 +0000 (01:02 +0000)
commit24f0469865686894a86091505330b0170ab30634
tree2d1d43cb3b20b8ca38cd24354522c595a1784f05
parent9e6378de5744088759f92a7503c7ca81d815c05d
[PPC64] Add vector pack/unpack support from ISA 2.07

This patch adds support for the following new instructions in the
Power ISA 2.07:

  vpksdss
  vpksdus
  vpkudus
  vpkudum
  vupkhsw
  vupklsw

These instructions are available through the vec_packs, vec_packsu,
vec_unpackh, and vec_unpackl built-in interfaces.  These are
lane-sensitive instructions, so the built-ins have different
implementations for big- and little-endian, and the instructions must
be marked as killing the vector swap optimization for now.

The first three instructions perform saturating pack operations.  The
fourth performs a modulo pack operation, which means it can be
represented with a vector shuffle, and conversely the appropriate
vector shuffles may cause this instruction to be generated.  The other
instructions are only generated via built-in support for now.

Appropriate tests have been added.

There is a companion patch to clang for the rest of this support.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@237499 91177308-0d34-0410-b5e6-96231b3b80d8
include/llvm/IR/IntrinsicsPowerPC.td
lib/Target/PowerPC/PPCISelLowering.cpp
lib/Target/PowerPC/PPCISelLowering.h
lib/Target/PowerPC/PPCInstrAltivec.td
lib/Target/PowerPC/PPCVSXSwapRemoval.cpp
test/CodeGen/PowerPC/vec_shuffle_p8vector.ll [new file with mode: 0644]
test/CodeGen/PowerPC/vec_shuffle_p8vector_le.ll [new file with mode: 0644]
test/MC/Disassembler/PowerPC/ppc64-encoding-p8vector.txt [new file with mode: 0644]
test/MC/PowerPC/ppc64-encoding-p8vector.s [new file with mode: 0644]