I'm introducing a new machine model to simultaneously allow simple
authorAndrew Trick <atrick@apple.com>
Sat, 7 Jul 2012 04:00:00 +0000 (04:00 +0000)
committerAndrew Trick <atrick@apple.com>
Sat, 7 Jul 2012 04:00:00 +0000 (04:00 +0000)
commit2661b411ccc81b1fe19194d3f43b2630cbef3f28
tree0decaebaee6c3a1a9d42df6b5619de1ffb2fac7d
parent06495cd7f2a91c4f659eac5e55b1c08b014d0a08
I'm introducing a new machine model to simultaneously allow simple
subtarget CPU descriptions and support new features of
MachineScheduler.

MachineModel has three categories of data:
1) Basic properties for coarse grained instruction cost model.
2) Scheduler Read/Write resources for simple per-opcode and operand cost model (TBD).
3) Instruction itineraties for detailed per-cycle reservation tables.

These will all live side-by-side. Any subtarget can use any
combination of them. Instruction itineraries will not change in the
near term. In the long run, I expect them to only be relevant for
in-order VLIW machines that have complex contraints and require a
precise scheduling/bundling model. Once itineraries are only actively
used by VLIW-ish targets, they could be replaced by something more
appropriate for those targets.

This tablegen backend rewrite sets things up for introducing
MachineModel type #2: per opcode/operand cost model.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159891 91177308-0d34-0410-b5e6-96231b3b80d8
27 files changed:
include/llvm/MC/MCInstrItineraries.h
include/llvm/MC/MCSchedule.h [new file with mode: 0644]
include/llvm/MC/MCSubtargetInfo.h
include/llvm/Target/Target.td
include/llvm/Target/TargetItinerary.td [new file with mode: 0644]
include/llvm/Target/TargetSchedule.td
lib/CodeGen/MachineScheduler.cpp
lib/CodeGen/ScoreboardHazardRecognizer.cpp
lib/CodeGen/SelectionDAG/ResourcePriorityQueue.cpp
lib/CodeGen/TargetInstrInfoImpl.cpp
lib/MC/MCSubtargetInfo.cpp
lib/Target/ARM/ARM.td
lib/Target/ARM/ARMScheduleA8.td
lib/Target/ARM/ARMScheduleA9.td
lib/Target/Hexagon/Hexagon.td
lib/Target/Hexagon/HexagonSchedule.td
lib/Target/Hexagon/HexagonScheduleV4.td
lib/Target/X86/X86.td
lib/Target/X86/X86Schedule.td
lib/Target/X86/X86ScheduleAtom.td
utils/TableGen/CMakeLists.txt
utils/TableGen/CodeGenSchedule.cpp [new file with mode: 0644]
utils/TableGen/CodeGenSchedule.h [new file with mode: 0644]
utils/TableGen/CodeGenTarget.cpp
utils/TableGen/CodeGenTarget.h
utils/TableGen/InstrInfoEmitter.cpp
utils/TableGen/SubtargetEmitter.cpp