clk: rockchip: rk3399: Add CLK_SET_RATE_PARENT for main VOP0
authorXing Zheng <zhengxing@rock-chips.com>
Thu, 7 Apr 2016 12:22:31 +0000 (20:22 +0800)
committerHuang, Tao <huangtao@rock-chips.com>
Wed, 13 Apr 2016 07:30:57 +0000 (15:30 +0800)
commit27d659372c590c843bd87e22d5e0502066bed45f
treeb55677e1d5f77c668785f7b8c7b032b48b6602bf
parent8d01ea2168124be2d9225c07d1812b149c1e24e4
clk: rockchip: rk3399: Add CLK_SET_RATE_PARENT for main VOP0

We recommend, VOP0 is the main screen, VOP1 is a sub screen,
only VOP0 is able to re-set parent (VPLL) rate.

Change-Id: If40f95ce18e73477df8f7f031013333a603d5eb2
Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
drivers/clk/rockchip/clk-rk3399.c