ARM: 6795/1: l2x0: Errata fix for flush by Way operation can cause data corrupti
authorSantosh Shilimkar <santosh.shilimkar@ti.com>
Tue, 8 Mar 2011 05:59:54 +0000 (06:59 +0100)
committerRussell King <rmk+kernel@arm.linux.org.uk>
Wed, 9 Mar 2011 00:18:34 +0000 (00:18 +0000)
commit2839e06c95d12ada034cf9b63da60334c7c6358b
tree9295f80025852f73fbf3c66740eae76df5d61314
parentd239b1dc093d551046a909920b5310c1d1e308c1
ARM: 6795/1: l2x0: Errata fix for flush by Way operation can cause data corrupti

PL310 implements the Clean & Invalidate by Way L2 cache maintenance
operation (offset 0x7FC). This operation runs in background so that
PL310 can handle normal accesses while it is in progress. Under very
rare circumstances, due to this erratum, write data can be lost when
PL310 treats a cacheable write transaction during a Clean & Invalidate
by Way operation.

Workaround:
Disable Write-Back and Cache Linefill (Debug Control Register)
Clean & Invalidate by Way (0x7FC)
Re-enable Write-Back and Cache Linefill (Debug Control Register)

This patch also removes any OMAP dependency on PL310 Errata's

Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Acked-by: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
arch/arm/Kconfig
arch/arm/include/asm/outercache.h
arch/arm/mm/cache-l2x0.c