InstCombine: mul to shl shouldn't preserve nsw
authorDavid Majnemer <david.majnemer@gmail.com>
Sat, 11 Oct 2014 10:19:52 +0000 (10:19 +0000)
committerDavid Majnemer <david.majnemer@gmail.com>
Sat, 11 Oct 2014 10:19:52 +0000 (10:19 +0000)
commit2af441e26e010e6c4b935d94f03fc8487e75f4b4
tree09f836dae3b1314243edab3b67a720e61cfe01e2
parent0b0126955ab2c944599693644c5069e12c90463e
InstCombine: mul to shl shouldn't preserve nsw

consider:
mul i32 nsw %x, -2147483648

this instruction will not result in poison if %x is 1

however, if we transform this into:
shl i32 nsw %x, 31

then we will be generating poison because we just shifted into the sign
bit.

This fixes PR21242.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@219566 91177308-0d34-0410-b5e6-96231b3b80d8
lib/Transforms/InstCombine/InstCombineMulDivRem.cpp
test/Transforms/InstCombine/2011-06-13-nsw-alloca.ll
test/Transforms/InstCombine/add2.ll
test/Transforms/InstCombine/cast.ll
test/Transforms/InstCombine/div.ll