[ARM] tegra: board-stingray: rearrange audio-clock sources

[ARM] tegra: board-stingray: rearrange audio-clock sources

-- Setting pll_a to 11.2896MHz breaks S/PDIF audio.  Setting it to
   56.448MHz fixes the problem.  This was working before because the
   pll_a settings were broken and attempting to set pll_a to
   11.2896MHz actually set it implcitly to 56.448MHz instead.
-- Reparent i2s.1 and i2s.2 to pll_p so that we can set them to 24MHz
   and 2MHz respectively.  This allows i2s.2 to talk to the Bluetooth
   controller at 8kHz glitch-free.
-- Remove initialization entries for clocks "audio" and "audio_2x";
   these clocks are not used by the audio driver any more.

Signed-off-by: Iliyan Malchev <malchev@google.com>