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(parent: d139c5d) | patch
AVX-512: shufflevector for i1 vectors <2 x i1> .. <64 x i1>
authorElena Demikhovsky <elena.demikhovsky@intel.com>
Thu, 17 Sep 2015 06:53:12 +0000 (06:53 +0000)
committerElena Demikhovsky <elena.demikhovsky@intel.com>
Thu, 17 Sep 2015 06:53:12 +0000 (06:53 +0000)
commit2e5bf5535ce4c9853c0c99c1fa795e747eb2232e
treef7e2d336f191d08a3a3b3b0940beebe0c5886d41tree | snapshot
parentd139c5d412156f29f3c250283be18f91c97effcfcommit | diff
AVX-512: shufflevector for i1 vectors <2 x i1> .. <64 x i1>
AVX-512 does not provide an instruction that shuffles mask register. So I do the following way:

mask-2-simd , shuffle simd , simd-2-mask

Differential Revision: http://reviews.llvm.org/D12727

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@247876 91177308-0d34-0410-b5e6-96231b3b80d8
lib/Target/X86/X86ISelLowering.cpp diff | blob | history
lib/Target/X86/X86InstrInfo.cpp diff | blob | history
test/CodeGen/X86/avx512-mask-op.ll diff | blob | history
test/CodeGen/X86/vector-shuffle-v1.ll [new file with mode: 0644] blob
C/C++ LLVM-based compilers that forbids OOTA behaviors