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[AArch64] Fix NZCV reg live-in bug in F128CSEL codegen.
authorAmara Emerson <amara.emerson@arm.com>
Thu, 24 Oct 2013 08:28:24 +0000 (08:28 +0000)
committerAmara Emerson <amara.emerson@arm.com>
Thu, 24 Oct 2013 08:28:24 +0000 (08:28 +0000)
commit2f21452ba1ee5bde8fee438b4cf1a1ce95beb6ca
tree125ba5dcedd49c3708aa083f3accc5817607d5b2tree | snapshot
parent5e4d8a5eca03c977ba01e061078a2d740ee6130acommit | diff
[AArch64] Fix NZCV reg live-in bug in F128CSEL codegen.

When generating the IfTrue basic block during the F128CSEL pseudo-instruction
handling, the NZCV live-in for the newly created BB wasn't being added. This
caused a fault during MI-sched/live range calculation when the predecessor
for the fall-through BB didn't have a live-in for phys-reg as expected.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193316 91177308-0d34-0410-b5e6-96231b3b80d8
lib/Target/AArch64/AArch64ISelLowering.cpp diff | blob | history
test/CodeGen/AArch64/regress-fp128-livein.ll [new file with mode: 0644] blob
C/C++ LLVM-based compilers that forbids OOTA behaviors