UPSTREAM: irqchip/gic-v3: Make sure read from ICC_IAR1_EL1 is visible on redestributor

UPSTREAM: irqchip/gic-v3: Make sure read from ICC_IAR1_EL1 is visible on redestributor

The ARM GICv3 specification mentions the need for dsb after a read
from the ICC_IAR1_EL1 register:

	4.1.1 Physical CPU Interface:
	The effects of reading ICC_IAR0_EL1 and ICC_IAR1_EL1
	on the state of a returned INTID are not guaranteed
	to be visible until after the execution of a DSB.

Not having this could result in missed interrupts, so let's add the
required barrier.

[Marc: fixed commit message]

Change-Id: I45f64990252b17a9e89ef69f3e53261b6af62ced
Acked-by: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Tirumalesh Chalamarla <tchalamarla@caviumnetworks.com>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Huang, Tao <huangtao@rock-chips.com>
(cherry picked from commit 1a1ebd5fb1e203ee8cc73508cc7a38ac4b804596)