drm/i915/skl: Stage the pipe DDB allocation
authorDamien Lespiau <damien.lespiau@intel.com>
Tue, 4 Nov 2014 17:07:01 +0000 (17:07 +0000)
committerDaniel Vetter <daniel.vetter@ffwll.ch>
Fri, 7 Nov 2014 17:42:14 +0000 (18:42 +0100)
commit34bb56af7fae9d4d6a33bf6f5f915e75a4023e02
tree9324f6fab1368a16f7cbd23b5ed5c9e51cfbe22e
parent5d374d9638924ff8c91a87f55dc895be7ab163f8
drm/i915/skl: Stage the pipe DDB allocation

To correctly flush the new DDB allocation we need to know about the pipe
allocation layout inside the DDB in order to sequence the re-allocation
to not cause a newly allocated pipe to fetch from a space that was
previously allocated to another pipe.

This patch preserves the per-pipe (start,end) allocation to be used in
the flush.

Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
drivers/gpu/drm/i915/i915_drv.h
drivers/gpu/drm/i915/intel_pm.c