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clk: rockchip: rk3228: fix some PLL_NUX_CLKs' gates
authorFinley Xiao <finley.xiao@rock-chips.com>
Thu, 22 Jun 2017 12:22:25 +0000 (20:22 +0800)
committerHuang, Tao <huangtao@rock-chips.com>
Fri, 23 Jun 2017 03:58:55 +0000 (11:58 +0800)
commit37648ee775bd823679ca5d77902ac6d5e283bf88
tree0a379f3bb19c86bff7687b6fd08ccb468f08f5c3tree | snapshot
parent011fafcfa0dd3c391fb8fd01edf1e2bbd7bc3b2fcommit | diff
clk: rockchip: rk3228: fix some PLL_NUX_CLKs' gates

Some PLL_NUX_CLKs' gates is actually behind muxs according to latest TRM,
so move the gates to composite clocks and amend their parent clocks.

Change-Id: Ib6043caa61e9df0473f2d0bdc756850968bb2a55
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
drivers/clk/rockchip/clk-rk3228.c diff | blob | history
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