[AArch64] Lower READCYCLECOUNTER using MRS PMCCTNR_EL0.

[AArch64] Lower READCYCLECOUNTER using MRS PMCCTNR_EL0.

This matches the ARM behavior. In both cases, the register is part
of the optional Performance Monitors extension, so, add the feature,
and enable it for the A-class processors we support.

Differential Revision: http://reviews.llvm.org/D12425

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@246555 91177308-0d34-0410-b5e6-96231b3b80d8