VX-512: Fixed a bug in FP logic operation lowering
authorElena Demikhovsky <elena.demikhovsky@intel.com>
Mon, 7 Dec 2015 14:33:34 +0000 (14:33 +0000)
committerElena Demikhovsky <elena.demikhovsky@intel.com>
Mon, 7 Dec 2015 14:33:34 +0000 (14:33 +0000)
commit3b45f263c3669c65a76f7033ee24093a9870cfcf
treea1fe35b7e29160e789d851d5239e7b3cff8bf5bd
parentfad998fc360e9d7140354e14ef71de8426446ead
VX-512: Fixed a bug in FP logic operation lowering

FP logic instructions are supported in DQ extension on AVX-512 target.
I use integer operations instead.
Added tests.
I also enabled FABS in this patch in order to check ANDPS.
The operations are FOR, FXOR, FAND, FANDN.
The instructions, that supported for 512-bit vector under DQ are:
VORPS/PD, VXORPS/PD, VANDPS/PD, FANDNPS/PD.

Differential Revision: http://reviews.llvm.org/D15110

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@254913 91177308-0d34-0410-b5e6-96231b3b80d8
lib/Target/X86/X86ISelLowering.cpp
lib/Target/X86/X86InstrInfo.td
lib/Target/X86/X86InstrSSE.td
test/CodeGen/X86/avx-logic.ll
test/CodeGen/X86/avx512-arith.ll
test/CodeGen/X86/vec_fabs.ll