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ARM: i.MX6Q: correct emi_sel clock muxing
authorLiu Ying <Ying.Liu@freescale.com>
Wed, 3 Jul 2013 07:29:06 +0000 (15:29 +0800)
committerShawn Guo <shawn.guo@linaro.org>
Mon, 15 Jul 2013 00:28:08 +0000 (08:28 +0800)
commit3b79cd15bfc5f1ddb5e387310fa3dbb09b81b552
tree85abb902178a907b7629dcf45f092f2ac305ec63tree | snapshot
parentceac9b9214df539ca814a784c2af94f554bc78d4commit | diff
ARM: i.MX6Q: correct emi_sel clock muxing

The correct muxing for emi_sel clock should be
2b'00 - 396M PFD
2b'01 - PLL3
2b'10 - AXI clk root
2b'11 - 352M PFD

This patch corrects the muxing in the clock driver.

Signed-off-by: Liu Ying <Ying.Liu@freescale.com>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Acked-by: Dirk Behme <dirk.behme@de.bosch.com>
arch/arm/mach-imx/clk-imx6q.c diff | blob | history
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