rk29: L2 cache设置变更。根据IC部的建议,810~972频率,data ram latency设为6 cycles
author黄涛 <huangtao@rock-chips.com>
Fri, 10 Dec 2010 10:05:40 +0000 (18:05 +0800)
committer黄涛 <huangtao@rock-chips.com>
Fri, 10 Dec 2010 10:05:40 +0000 (18:05 +0800)
commit40a1ab5ca92ccda7cdbd88df6942e596c0702611
tree6901d885f9ffcb910c05fe4689fd61e21e2a6faa
parentd1d5fd00f5ab78c5c5edc9f0f7529ce0408244d3
rk29: L2 cache设置变更。根据IC部的建议,810~972频率,data ram latency设为6 cycles
arch/arm/mm/proc-v7.S