drm/i915: Enable eDP DRRS for CHV
authorDurgadoss R <durgadoss.r@intel.com>
Fri, 13 Feb 2015 10:03:02 +0000 (15:33 +0530)
committerDaniel Vetter <daniel.vetter@ffwll.ch>
Tue, 24 Feb 2015 10:51:38 +0000 (11:51 +0100)
commit44395bfe2f2a22ec769eb51ea1908082cf9aa16d
tree24399eb6afe56a9a213fab97f9d85c165e2a6d01
parent6fa7aec1db07f43d3ad94122c3bd52647c81619e
drm/i915: Enable eDP DRRS for CHV

This patch enables eDP DRRS for CHV by adding the
required IS_CHERRYVIEW() checks.
CHV uses the same register bit as VLV.

[Vandana]: Since CHV has 2 sets of M_N registers, it will follow the same code
path as gen < 8. Added CHV check in dp_set_m_n()

[Ram]: Rebased on top of previous patch modifications

Signed-off-by: Durgadoss R <durgadoss.r@intel.com>
Signed-off-by: Vandana Kannan <vandana.kannan@intel.com>
Signed-off-by: Ramalingam C <ramalingam.c@intel.com>
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
drivers/gpu/drm/i915/intel_display.c
drivers/gpu/drm/i915/intel_dp.c