Add first bunch of SPE instructions. As they overlap with Altivec, mark
authorJoerg Sonnenberger <joerg@bec.de>
Thu, 7 Aug 2014 12:18:21 +0000 (12:18 +0000)
committerJoerg Sonnenberger <joerg@bec.de>
Thu, 7 Aug 2014 12:18:21 +0000 (12:18 +0000)
commit445a9f97295b86e6222c030facaaee34398c9757
treedb20a8c48521d0f57b64335ee644ab1ab72c8ae9
parent2ca1dd1381e0bb709a0c043847eb4817280bf529
Add first bunch of SPE instructions. As they overlap with Altivec, mark
them as parser-only until the disassembler is extended to handle
predicates properly.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@215102 91177308-0d34-0410-b5e6-96231b3b80d8
lib/Target/PowerPC/PPC.td
lib/Target/PowerPC/PPCInstrInfo.td
lib/Target/PowerPC/PPCInstrSPE.td [new file with mode: 0644]
lib/Target/PowerPC/PPCSubtarget.cpp
lib/Target/PowerPC/PPCSubtarget.h
test/MC/PowerPC/ppc64-encoding-spe.s [new file with mode: 0644]