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ARM: dts: berlin2q: set L2CC tag and data latency to 2 cycles
authorJisheng Zhang <jszhang@marvell.com>
Thu, 12 Jun 2014 09:38:40 +0000 (17:38 +0800)
committerSebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Mon, 16 Jun 2014 11:09:04 +0000 (13:09 +0200)
commit44991eb4bfd63b043b50e880d347a7946d6a9736
tree8fcacf5483a5efe8b605521867cdbc72fc1c3edetree | snapshot
parent7171511eaec5bf23fb06078f59784a3a0626b38fcommit | diff
ARM: dts: berlin2q: set L2CC tag and data latency to 2 cycles

For all BG2Q SoCs, 2 cycles is the best/correct value.

Signed-off-by: Jisheng Zhang <jszhang@marvell.com>
Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
arch/arm/boot/dts/berlin2q.dtsi diff | blob | history
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