Select an OR with immediate as an ADD if the input bits are known zero. This allow...
authorEvan Cheng <evan.cheng@apple.com>
Mon, 11 Jan 2010 17:03:47 +0000 (17:03 +0000)
committerEvan Cheng <evan.cheng@apple.com>
Mon, 11 Jan 2010 17:03:47 +0000 (17:03 +0000)
commit4b0345be3071a5612023588eef689b93f3e94fa4
tree8b00fa6a2e6aacbf0e0ea788a5fb786a45930045
parent95eb2eeea65fbae223ffd517f3984f14b034fcb8
Select an OR with immediate as an ADD if the input bits are known zero. This allow the instruction to be 3address-fied if needed.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@93152 91177308-0d34-0410-b5e6-96231b3b80d8
lib/Target/X86/X86Instr64bit.td
lib/Target/X86/X86InstrInfo.td
test/CodeGen/X86/2009-05-23-dagcombine-shifts.ll
test/CodeGen/X86/3addr-or.ll [new file with mode: 0644]