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ARM: vexpress/dcscb: fix cache disabling sequences
authorNicolas Pitre <nicolas.pitre@linaro.org>
Wed, 17 Jul 2013 00:59:53 +0000 (20:59 -0400)
committerJon Medhurst <tixy@linaro.org>
Mon, 2 Dec 2013 12:54:16 +0000 (12:54 +0000)
commit4c35ee5ab39fb4ab30662edbfc7b6ea5c88943f2
tree735c73e6bc06cd8356a8dfa6b05d7a94c373f67etree | snapshot
parent493c65aab4cfbdec1b065d409fd8b2c9b907d8eccommit | diff
ARM: vexpress/dcscb: fix cache disabling sequences

Commit e8f9bb1bd6bb93fff773345cc54c42585e0e3ece upstream

Unlike real A15/A7's, the RTSM simulation doesn't appear to hit the
cache when the CTRL.C bit is cleared.  Let's ensure there is no memory
access within the disable and flush cache sequence, including to the
stack.

Signed-off-by: Nicolas Pitre <nico@linaro.org>
Signed-off-by: Jon Medhurst <tixy@linaro.org>
arch/arm/mach-vexpress/dcscb.c diff | blob | history
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