ARM: Improve the L2 cache performance when PL310 is used

ARM: Improve the L2 cache performance when PL310 is used

With this L2 cache controller, the cache maintenance by PA and sync
operations are atomic and do not require a "wait" loop or spinlocks.
This patch conditionally defines the cache_wait() function and locking
primitives (rather than duplicating the functions or file).

Since L2x0 cache controllers do not work with ARMv7 CPUs, the patch
automatically enables CACHE_PL310 when CPU_V7 is defined.

Change-Id: I23e8fc326e6c42e7b36c7b67393fa91576692b48
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>