drm: bridge: dw-hdmi: Reorder HDMI Initialization Step

drm: bridge: dw-hdmi: Reorder HDMI Initialization Step

There is a bug of pll lock detection in previous code.

/* Wait for PHY PLL lock */
msec = 5;
do {
	val = hdmi_readb(hdmi, HDMI_PHY_STAT0) & HDMI_PHY_TX_PHY_LOCK;
	if (!val)
		break;
	...
} while (1)

while is break if pll is not lock yet, the real lock status may
be after the dw_hdmi_enable_video_path.

This bug is fixed in commit <a479fa5417b12fdf7aef8e41fdb99393e1c28581>
(FROMLIST: drm: bridge: dw-hdmi: Fix the PHY power up sequence)

But it introduced an new bug: hdmi output timing may be not stable,
the format shown on some TV is not a standard hdmi timing. For example,
1080P will be shown as 1922x1080 on LEADSTAR LD-1088.

After reorder the HDMI Initialization Step, phy initialization is
moved after the dw_hdmi_enable_video_path, this bug is fixed.

Change-Id: Id996978ceabcf1cce4bf83ddb84528c04fbb7583
Signed-off-by: Zheng Yang <zhengyang@rock-chips.com>