Add test case to verify correct relocs being generated for
authorUlrich Weigand <ulrich.weigand@de.ibm.com>
Tue, 13 Nov 2012 21:53:43 +0000 (21:53 +0000)
committerUlrich Weigand <ulrich.weigand@de.ibm.com>
Tue, 13 Nov 2012 21:53:43 +0000 (21:53 +0000)
commit51abc9877e229bddf258d24386ab8d394e93ac33
tree2dd5da57bbf4b0958b988160fd2a2b4950e2079e
parenta8028e58844a544cb0fe4f27c580b1e861f1d3e5
Add test case to verify correct relocs being generated for
TLS symbols on PowerPC using the integrated assembler.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167875 91177308-0d34-0410-b5e6-96231b3b80d8
test/MC/PowerPC/ppc64-tls-relocs-01.ll [new file with mode: 0644]