Fix logic inversion for RI-mode address selection
authorAnton Korobeynikov <asl@math.spbu.ru>
Thu, 16 Jul 2009 14:31:14 +0000 (14:31 +0000)
committerAnton Korobeynikov <asl@math.spbu.ru>
Thu, 16 Jul 2009 14:31:14 +0000 (14:31 +0000)
commit54681eca6900295a5592fba82ccf6120e0a65db2
treefcf77d94d458595968d7425c18187af12304727d
parent9419a0d13df0923fb5009bd4158e4d2347ed27ea
Fix logic inversion for RI-mode address selection

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76052 91177308-0d34-0410-b5e6-96231b3b80d8
lib/Target/SystemZ/SystemZISelDAGToDAG.cpp
test/CodeGen/SystemZ/2009-07-11-InvalidRIISel.ll [new file with mode: 0644]