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(parent: 9eb856b) | patch
Don't cache the instruction and register info from the TargetMachine, because
authorBill Wendling <isanbard@gmail.com>
Fri, 7 Jun 2013 06:19:56 +0000 (06:19 +0000)
committerBill Wendling <isanbard@gmail.com>
Fri, 7 Jun 2013 06:19:56 +0000 (06:19 +0000)
commit54a56fad36a32f12709da5f96998336f08524be9
treeb8ff9ae26a5ebd885ba1a05b8b9934b04bca9e6etree | snapshot
parent9eb856bc295eabe1ebff0325158e65050deddd56commit | diff
Don't cache the instruction and register info from the TargetMachine, because
the internals of TargetMachine could change.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183490 91177308-0d34-0410-b5e6-96231b3b80d8
lib/Target/Hexagon/HexagonCallingConvLower.cpp diff | blob | history
lib/Target/Hexagon/HexagonCallingConvLower.h diff | blob | history
lib/Target/Hexagon/HexagonISelDAGToDAG.cpp diff | blob | history
lib/Target/Hexagon/HexagonInstrInfo.cpp diff | blob | history
lib/Target/Hexagon/HexagonInstrInfo.h diff | blob | history
lib/Target/Hexagon/HexagonMachineScheduler.cpp diff | blob | history
lib/Target/Hexagon/HexagonMachineScheduler.h diff | blob | history
lib/Target/Hexagon/HexagonRegisterInfo.cpp diff | blob | history
lib/Target/Hexagon/HexagonRegisterInfo.h diff | blob | history
C/C++ LLVM-based compilers that forbids OOTA behaviors