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(parent: b32e784) | patch
Make RegList an ASM operand so that TableGen will generate code for it. This is
authorBill Wendling <isanbard@gmail.com>
Mon, 8 Nov 2010 00:39:58 +0000 (00:39 +0000)
committerBill Wendling <isanbard@gmail.com>
Mon, 8 Nov 2010 00:39:58 +0000 (00:39 +0000)
commit5991487c10faa5f1c0cc815381d745150582a309
tree064f00b9585dd15aee5ef4ae63e5baa5353abc43tree | snapshot
parentb32e7844e9f79d2bd4ff34a1d19aba347f999abccommit | diff
Make RegList an ASM operand so that TableGen will generate code for it. This is
an initial implementation and may change once reglists are fully fleshed out.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118390 91177308-0d34-0410-b5e6-96231b3b80d8
lib/Target/ARM/ARMInstrInfo.td diff | blob | history
C/C++ LLVM-based compilers that forbids OOTA behaviors