[ARM] Add instruction selection patterns for vmin/vmax
Summary:
The mid-end was generating vector smin/smax/umin/umax nodes, but
we were using vbsl to generatate the code. This adds the vmin/vmax
patterns and a test to check that we are now generating vmin/vmax
instructions.
Reviewers: rengolin, jmolloy
Subscribers: aemerson, rengolin, llvm-commits
Differential Revision: http://reviews.llvm.org/D12105
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@245439
91177308-0d34-0410-b5e6-
96231b3b80d8
projects / oota-llvm.git / commit