UPSTREAM: clk: Add clk_composite_set_rate_and_parent

UPSTREAM: clk: Add clk_composite_set_rate_and_parent

When changing the clock-rate, currently a new parent is set first and a
divider adapted thereafter. This may result in the clock-rate overflowing
its target rate for a short time if the new parent has a higher rate than
the old parent.

While this often doesn't produce negative effects, it can affect components
in a voltage-scaling environment, like the GPU on the rk3399 socs, where
the voltage than simply is to low for the temporarily to high clock rate.

For general clock hirarchies this may need more extensive adaptions to
the common clock-framework, but at least for composite clocks having
both parent and rate settings it is easy to create a short-term solution to
make sure the clock-rate does not overflow the target.

Change-Id: Iceb40b24ef13db6947be3d797ea90b3e1055b9df
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
Reviewed-by: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
(cherry picked from git.kernel.org clk/linux.git clk-next
 commit 9e52cec04fd3b9b686f9256151b47fe61f7c28ef)