clk: rk3368: add clk_pll_ops_3368_low_jitter and modify dclk_lcdc ops

clk: rk3368: add clk_pll_ops_3368_low_jitter and modify dclk_lcdc ops

In order to provide low jitter dclk_lcdc for dislay(especially HDMI),
we neeed to set dclk_lcdc's src pll with max VCO. Thus we add
clk_pll_ops_3368_low_jitter type pll to get pll low jitter setting
from a table. Also dclk_lcdc ops in rk3368 is modifided to get best
parent rate from a table firstly, or caculate a parent rate if not
found in the table.

Signed-off-by: dkl <dkl@rock-chips.com>