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(parent: 7617d4a) | patch
rk2928: l2 data ram latency, write 1 cycle, read 3 cycles, setup 2 cycles
author黄涛 <huangtao@rock-chips.com>
Wed, 8 Aug 2012 03:25:30 +0000 (11:25 +0800)
committer黄涛 <huangtao@rock-chips.com>
Wed, 8 Aug 2012 03:25:30 +0000 (11:25 +0800)
commit64340b93df27c256053ab01a0e5dafabd1fe1d8f
tree8162d4f65f86111c71f72707fb65e0beb98204c1tree | snapshot
parent7617d4a3e601feafa85fb658f59c0493d73b48f6commit | diff
rk2928: l2 data ram latency, write 1 cycle, read 3 cycles, setup 2 cycles
arch/arm/mach-rk2928/common.c diff | blob | history
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