[PowerPC] Fix and(or(x, c1), c2) -> rlwimi generation

[PowerPC] Fix and(or(x, c1), c2) -> rlwimi generation

PPCISelDAGToDAG has a transformation that generates a rlwimi instruction from
an input pattern that looks like this:

  and(or(x, c1), c2)

but the associated logic does not work if there are bits that are 1 in c1 but 0
in c2 (these are normally canonicalized away, but that can't happen if the 'or'
has other users. Make sure we abort the transformation if such bits are
discovered.

Fixes PR24704.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@246900 91177308-0d34-0410-b5e6-96231b3b80d8