irqchip/gic-v3: Specialize readq and writeq accesses
authorJean-Philippe Brucker <jean-philippe.brucker@arm.com>
Thu, 1 Oct 2015 12:47:16 +0000 (13:47 +0100)
committerMarc Zyngier <marc.zyngier@arm.com>
Fri, 9 Oct 2015 22:11:53 +0000 (23:11 +0100)
commit72c971262f00185b4c6208812645c3feab4c77a3
treef7ad8284958cf10eaf5b009074e367aa5663b825
parentf6c86a41e1dc2214363b00cc0eadb8a5401c892d
irqchip/gic-v3: Specialize readq and writeq accesses

On 32bit platforms, we cannot assure that an I/O ldrd or strd will be
done atomically. Besides, an hypervisor would be unable to emulate such
accesses.
In order to allow the AArch32 version of the driver to split them into
two 32bit accesses while keeping the requirement for atomic writes, this
patch specializes the IROUTER and TYPER accesses.
Since the latter is an ID register, it won't need to be read atomically,
but we still avoid future confusion by using gic_read_typer instead of a
generic gic_readq.

Reviewed-by: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Jean-Philippe Brucker <jean-philippe.brucker@arm.com>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
arch/arm64/include/asm/arch_gicv3.h
drivers/irqchip/irq-gic-v3.c