clk: rockchip: rk3288: adjust clock settings
authordkl <dkl@rock-chips.com>
Sun, 20 Apr 2014 13:19:13 +0000 (21:19 +0800)
committerdkl <dkl@rock-chips.com>
Mon, 28 Apr 2014 13:24:24 +0000 (21:24 +0800)
commit7348c1bed5da5654b9eefb79881910905d0a57a5
tree723416cb6b106c081c4b60b74375d5f2601901f0
parent91019ca759b259519a96d3916a441bdf2004cf6f
clk: rockchip: rk3288: adjust clock settings

1. add clkops_rate_3288_dclk_lcdc0/1
2. change gpll init_rate to 297M, and npll init_rate to 1250M
arch/arm/boot/dts/rk3288-clocks.dtsi
arch/arm/boot/dts/rk3288.dtsi
drivers/clk/rockchip/clk-ops.c
drivers/clk/rockchip/clk-pll.c
include/dt-bindings/clock/rockchip.h