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(parent: b8bf5d7) | patch
drm/i915: don't enable FBC when pixel rate exceeds 95% on HSW/BDW
authorPaulo Zanoni <paulo.r.zanoni@intel.com>
Mon, 14 Sep 2015 18:19:59 +0000 (15:19 -0300)
committerDaniel Vetter <daniel.vetter@ffwll.ch>
Wed, 23 Sep 2015 12:39:18 +0000 (14:39 +0200)
commit7b24c9a696c1c68eaa471a27bf467e97a9986fa9
treeb71211080b31619a8c95c4c437b641823af8f3f0tree | snapshot
parentb8bf5d7fe0dee64ed0a73fa1e95ba8e464d605dacommit | diff
drm/i915: don't enable FBC when pixel rate exceeds 95% on HSW/BDW

BSpec says we shouldn't enable FBC on HSW/BDW when the pipe pixel rate
exceeds 95% of the core display clock.

v2:
  - HSW also needs the WA (Ville).
  - Add the WA name (Ville).
  - Use the current cdclk (Ville).

Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
drivers/gpu/drm/i915/i915_drv.h diff | blob | history
drivers/gpu/drm/i915/intel_fbc.c diff | blob | history
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