Allow targets which produce setcc results in non-MVT::i1 registers to describe

Allow targets which produce setcc results in non-MVT::i1 registers to describe
what the contents of the top bits of these registers are, in the common cases
of targets that sign and zero extend the results.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21145 91177308-0d34-0410-b5e6-96231b3b80d8