Make sure no loads resulting from load->switch DAGCombine are marked invariant
authorLouis Gerbarg <lgg@apple.com>
Thu, 31 Jul 2014 21:45:05 +0000 (21:45 +0000)
committerLouis Gerbarg <lgg@apple.com>
Thu, 31 Jul 2014 21:45:05 +0000 (21:45 +0000)
commit7d54c5b0f2d4923c58ba8cf70d0526cc24783fc6
treec197700c0132e263cf54bcb6fe518358b038b484
parentf7be7f15c1ff2882719f823fbe270e48bb0f4340
Make sure no loads resulting from load->switch DAGCombine are marked invariant

Currently when DAGCombine converts loads feeding a switch into a switch of
addresses feeding a load the new load inherits the isInvariant flag of the left
side. This is incorrect since invariant loads can be reordered in cases where it
is illegal to reoarder normal loads.

This patch adds an isInvariant parameter to getExtLoad() and updates all call
sites to pass in the data if they have it or false if they don't. It also
changes the DAGCombine to use that data to make the right decision when
creating the new load.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214449 91177308-0d34-0410-b5e6-96231b3b80d8
19 files changed:
include/llvm/CodeGen/SelectionDAG.h
lib/CodeGen/SelectionDAG/DAGCombiner.cpp
lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp
lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
lib/CodeGen/SelectionDAG/SelectionDAG.cpp
lib/Target/AArch64/AArch64ISelLowering.cpp
lib/Target/ARM/ARMISelLowering.cpp
lib/Target/Mips/MipsISelLowering.cpp
lib/Target/NVPTX/NVPTXISelLowering.cpp
lib/Target/PowerPC/PPCISelLowering.cpp
lib/Target/R600/AMDGPUISelLowering.cpp
lib/Target/R600/R600ISelLowering.cpp
lib/Target/Sparc/SparcISelLowering.cpp
lib/Target/SystemZ/SystemZISelLowering.cpp
lib/Target/X86/X86ISelDAGToDAG.cpp
lib/Target/X86/X86ISelLowering.cpp
lib/Target/XCore/XCoreISelLowering.cpp