[X86, AVX] try to lowerVectorShuffleAsElementInsertion() for all 256-bit vector sub...
authorSanjay Patel <spatel@rotateright.com>
Tue, 31 Mar 2015 16:32:11 +0000 (16:32 +0000)
committerSanjay Patel <spatel@rotateright.com>
Tue, 31 Mar 2015 16:32:11 +0000 (16:32 +0000)
commit7ea151449d5d932c92aa09b917e7e5801455947d
tree64bd3e0051d6d61c03798a1743964d16b1909b96
parent360fb1b93b4b362cf5db1ce5d0ffce8535ff7425
[X86, AVX] try to lowerVectorShuffleAsElementInsertion() for all 256-bit vector sub-types

I suggested this change in D7898 (http://llvm.org/viewvc/llvm-project?view=revision&revision=231354)

It improves the v4i64 case although not optimally. This AVX codegen:

  vmovq {{.*#+}} xmm0 = mem[0],zero
  vxorpd %ymm1, %ymm1, %ymm1
  vblendpd {{.*#+}} ymm0 = ymm0[0],ymm1[1,2,3]

Becomes:

  vmovsd {{.*#+}} xmm0 = mem[0],zero

Unfortunately, this doesn't completely solve PR22685. There are still at least 2 problems under here:

    We're not handling v32i8 / v16i16.
    We're not getting the FP / int domains right for instruction selection.

But since this patch alone appears to do no harm, reduces code duplication, and helps v4i64,
I'm submitting this patch ahead of fixing the above.

Differential Revision: http://reviews.llvm.org/D8341

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@233704 91177308-0d34-0410-b5e6-96231b3b80d8
lib/Target/X86/X86ISelLowering.cpp
test/CodeGen/X86/2012-1-10-buildvector.ll
test/CodeGen/X86/vector-shuffle-256-v4.ll
test/CodeGen/X86/vector-shuffle-256-v8.ll