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[AArch64] Extend the number of scalar instructions supported in the AdvSIMD
authorChad Rosier <mcrosier@codeaurora.org>
Mon, 4 Aug 2014 21:20:25 +0000 (21:20 +0000)
committerChad Rosier <mcrosier@codeaurora.org>
Mon, 4 Aug 2014 21:20:25 +0000 (21:20 +0000)
commit82c93451f3107b446d93a9d987f8dddab134b30f
tree93c7b8e742d1c772d423429aa0023e398aaee95ctree | snapshot
parenta770bd6cae66b591cf9b1f1fa9da0df78ec57df9commit | diff
[AArch64] Extend the number of scalar instructions supported in the AdvSIMD
scalar integer instruction pass.

This is a patch I had lying around from a few months ago.  The pass is
currently disabled by default, so nothing to interesting.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214779 91177308-0d34-0410-b5e6-96231b3b80d8
lib/Target/AArch64/AArch64AdvSIMDScalarPass.cpp diff | blob | history
test/CodeGen/AArch64/arm64-AdvSIMD-Scalar.ll diff | blob | history
C/C++ LLVM-based compilers that forbids OOTA behaviors