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arm: tcc8k: Choose PLL settings conforming to board layout
authorOskar Schirmer <oskar@linutronix.de>
Thu, 17 Feb 2011 15:42:58 +0000 (16:42 +0100)
committerThomas Gleixner <tglx@linutronix.de>
Fri, 11 Mar 2011 09:06:05 +0000 (10:06 +0100)
commit85922e54a3a14a6aee6c0b1fc67d81ef0c60fc9c
tree7ad5d37246e948424769c0456cd7d09f95f0192etree | snapshot
parent30d913556b25db11f2537f4412487c6e81dc0374commit | diff
arm: tcc8k: Choose PLL settings conforming to board layout

The evaluation board is driven with 1.2V core voltage, so system clock
must not exceed 192 MHz, bus clock must not exceed 110 MHz. Choose
appropriate values and set DTCMWAIT accordingly. Adapt UART setting to
avoid console log interruption and wait for the specified locking time
of 300us to pass.

Signed-off-by: Oskar Schirmer <oskar@linutronix.de>
Cc: bigeasy@linutronix.de
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
arch/arm/mach-tcc8k/board-tcc8000-sdk.c diff | blob | history
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