vdpu clk set 300Mhz,dclk_lcdc 27Mhz is form gpll instead of extern 27MHz
authorxxx <xxx@rock-chips.com>
Mon, 9 Apr 2012 05:14:40 +0000 (22:14 -0700)
committerxxx <xxx@rock-chips.com>
Mon, 9 Apr 2012 05:14:40 +0000 (22:14 -0700)
commit860797af0b9fefc9f67377dcadc9866dd3be8d46
tree00b4dd8e9b0ca62c3cf1c12848fefdff46afac8c
parent8e6e5648c66dbbe6db14c41b0ab7df12cf9081d5
vdpu clk set 300Mhz,dclk_lcdc 27Mhz is form gpll instead of extern 27MHz
arch/arm/mach-rk30/clock.c
arch/arm/mach-rk30/clock_data.c
arch/arm/mach-rk30/include/mach/board.h