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[InstCombine][X86][SSE] Replace sign/zero extension intrinsics with native IR
authorSimon Pilgrim <llvm-dev@redking.me.uk>
Mon, 27 Jul 2015 18:52:15 +0000 (18:52 +0000)
committerSimon Pilgrim <llvm-dev@redking.me.uk>
Mon, 27 Jul 2015 18:52:15 +0000 (18:52 +0000)
commit8e2e33527641f1e72eaaeb15daa87f0f9160e42e
treec0600cc4121aaff44fa7fc7101dd8c648e27a7actree | snapshot
parent2deaa2924e52f1e07102b395302e8a72d92d716ccommit | diff
[InstCombine][X86][SSE] Replace sign/zero extension intrinsics with native IR

Now that we are generating sane codegen for vector sext/zext nodes on SSE targets, this patch uses instcombine to replace the SSE41/AVX2 pmovsx and pmovzx intrinsics with the equivalent native IR code.

Differential Revision: http://reviews.llvm.org/D11503

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@243303 91177308-0d34-0410-b5e6-96231b3b80d8
lib/Transforms/InstCombine/InstCombineCalls.cpp diff | blob | history
test/Transforms/InstCombine/vec_demanded_elts.ll diff | blob | history
test/Transforms/InstCombine/x86-pmovsx.ll [new file with mode: 0644] blob
test/Transforms/InstCombine/x86-pmovzx.ll [new file with mode: 0644] blob
C/C++ LLVM-based compilers that forbids OOTA behaviors