[x86] Teach the AVX1 path of the new vector shuffle lowering one more
authorChandler Carruth <chandlerc@gmail.com>
Tue, 23 Sep 2014 10:08:29 +0000 (10:08 +0000)
committerChandler Carruth <chandlerc@gmail.com>
Tue, 23 Sep 2014 10:08:29 +0000 (10:08 +0000)
commit8f637786d825f631ecdd58e3c773f06505310048
tree026457e7f3155db6e325f1533bf96f11acc4e30a
parent5f843038fbc274615ddc113e421c379552e212c8
[x86] Teach the AVX1 path of the new vector shuffle lowering one more
trick that I missed.

VPERMILPS has a non-immediate memory operand mode that allows it to do
asymetric shuffles in the two 128-bit lanes. Use this rather than two
shuffles and a blend.

However, it turns out the variable shuffle path to VPERMILPS (and
VPERMILPD, although that one offers no functional differenc from the
immediate operand other than variability) wasn't even plumbed through
codegen. Do such plumbing so that we can reasonably emit
a variable-masked VPERMILP instruction. Also plumb basic comment parsing
and printing through so that the tests are reasonable.

There are still a few tests which don't show the shuffle pattern. These
are tests with undef lanes. I'll teach the shuffle decoding and printing
to handle undef mask entries in a follow-up. I've looked at the masks
and they seem reasonable.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@218300 91177308-0d34-0410-b5e6-96231b3b80d8
lib/Target/X86/Utils/X86ShuffleDecode.cpp
lib/Target/X86/Utils/X86ShuffleDecode.h
lib/Target/X86/X86ISelLowering.cpp
lib/Target/X86/X86ISelLowering.h
lib/Target/X86/X86InstrFragmentsSIMD.td
lib/Target/X86/X86InstrSSE.td
lib/Target/X86/X86MCInstLower.cpp
test/CodeGen/X86/vector-shuffle-256-v8.ll