drm/i915: Avoid div by zero when pixel clock is large
authorVille Syrjälä <ville.syrjala@linux.intel.com>
Fri, 14 Feb 2014 12:18:57 +0000 (14:18 +0200)
committerDaniel Vetter <daniel.vetter@ffwll.ch>
Fri, 7 Mar 2014 21:36:58 +0000 (22:36 +0100)
commit922044c9dfec40d5adc5d4a757f802e55e3d0a85
tree5e3700d4f1837b652b600038c32da3a4c9efeceb
parent77961eb984c7e5394bd29cc7be2ab0bf0cc7e7b1
drm/i915: Avoid div by zero when pixel clock is large

Make sure the line_time_us isn't zero in the gmch watermarks code as
that would cause a div by zero. This can be triggered by specifying
a very fast pixel clock for the mode.

At some point we should probably just switch over to using the same
math we use on PCH platforms which avoids such intermediate rounded
results.

Also we should verify the user provided mode much more rigorously.
At the moment we accept pretty much anything.

Note that "very fast mode" here means above 74.25 GHz.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
[danvet: Add Ville's clarification of what "very fast" means.]
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
drivers/gpu/drm/i915/intel_pm.c