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(parent: 5abdbf2) | patch
clk: sunxi: Add support for PLL6 on the A31
authorMaxime Ripard <maxime.ripard@free-electrons.com>
Wed, 5 Feb 2014 13:05:03 +0000 (14:05 +0100)
committerEmilio López <emilio@elopez.com.ar>
Tue, 18 Feb 2014 12:45:13 +0000 (09:45 -0300)
commit92ef67c53ad92487c3c8de75e7940384c2edd793
treeca846e52a7c9183ef4038399e5c8d098bbba8827tree | snapshot
parent5abdbf2f497c1769aa9df284ad125d40641207c7commit | diff
clk: sunxi: Add support for PLL6 on the A31

The A31 has a slightly different PLL6 clock. Add support for this new clock in
our driver.

Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: Emilio López <emilio@elopez.com.ar>
Documentation/devicetree/bindings/clock/sunxi.txt diff | blob | history
drivers/clk/sunxi/clk-sunxi.c diff | blob | history
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